data sheet 26185.121 8-bit serial-input, dmos power driver the A6A595KA and a6a595klb combine an 8-bit cmos shift register and accompanying data latches, control circuitry, and dmos power driver outputs. power driver applications include relays, sole- noids, and other medium-current or high-voltage peripheral power loads. the serial-data input, cmos shift register and latches allow direct interfacing with microprocessor-based systems. serial-data input rates are over 5 mhz. use with ttl may require appropriate pull-up resistors to ensure an input logic high. a cmos serial-data output enables cascade connections in appli- cations requiring additional drive lines. the a6a595 dmos open-drain outputs are capable of sinking up to 500 ma. all of the output drivers are disabled (the dmos sink drivers turned off) by the output enable input high. the A6A595KA is furnished in a 20-pin dual in-line plastic package. the a6a595klb is furnished in a 24-lead wide-body, small- outline plastic batwing package (soic) with gull-wing leads. copper lead frames, reduced supply current requirements, and low on-state resistance allow both devices to sink 150 ma from all outputs continu- ously, to ambient temperatures over 85 c. features 50 v minimum output clamp voltage 350 ma output current (all outputs simultaneously) 1 ? typical r ds(on) internal short-circuit protection low power consumption replacements for tpic6a595n and tpic6a595dw 6a595 preliminary information (subject to change without notice) june 11, 2001 always order by complete part number: part number package r ja r jc r jt A6A595KA 20-pin dip55 c/w 25 c/w a6a595klb 24-lead soic 55 c/w 6 c/w absolute maximum ratings at t a = 25 c output voltage, v o ............................... 50 v output drain current, continuous, i o .......................... 350 ma * peak, i om ................................. 1100 ma? single-pulse avalanche energy, e as .. 75 mj avalanche current, i as ..................... 600 ma source-drain diode current, i fm ............ 2 a logic supply voltage, v dd .................. 7.0 v input voltage range, v i ..... -0.3 v to +7.0 v package power dissipation, p d ... see graph junction temperature, t j .................. +150 c operating temperature range, t a ................................. -40 c to +125 c storage temperature range, t s ................................. -55 c to +150 c * each output, all outputs on. ? pulse duration 100 s, duty cycle 2%. caution: these cmos devices have input static protection (class 3) but are still susceptible to damage if exposed to extremely high static electrical charges. latches register serial data in register clear out 3 v dd strobe clock clk st dwg. pp-029-15 out 2 output enable oe logic ground clr 13 14 15 16 17 19 12 18 20 11 1 2 3 8 9 4 5 6 7 10 power ground power ground power ground power ground out 5 out 4 out 6 out 7 out 1 out 0 serial data out logic supply register latches A6A595KA (dip)
6a595 8-bit serial-input, dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 2 copyright ?2000, allegro microsystems, inc. functional block diagram power ground dwg. fp-013-6 out 0 out n power ground clock serial data in strobe output enable (active low) serial data out serial-parallel shift register d-type latches v dd logic supply register clear (active low) logic ground current limit and charge pump sub power grounds must be connected together externally. power ground power ground power ground power ground power ground power ground power ground power ground latches register serial data in register clear out 3 v dd strobe clock clk st dwg. pp-029-16a out 2 output enable oe logic ground clr out 5 out 4 out 6 out 7 out 1 out 0 serial data out logic supply register latches 1 2 3 817 18 19 20 21 23 4 5 6 7 22 24 12 9 10 11 13 14 15 16 a6a595klb (soic) 50 75 100 125 150 5 1 0 allowable package power dissipation in watts temperature in c 4 3 2 25 dwg. gp-049-5 suffix 'lb', r = 6.0 c/w jt r = 55 c/w ja suffix 'a', r = 25 c/w jc
6a595 8-bit serial-input, dmos power driver www.allegromicro.com 3 truth table shift register contents serial latch contents output contents data clock data output input input i 0 i 1 i 2 ... i 6 i 7 output strobe i 0 i 1 i 2 ... i 6 i 7 enable i 0 i 1 i 2 i 6 i 7 hhr 0 r 1 r 5 r 6 r 6 llr 0 r 1 r 5 r 6 r 6 xr 0 r 1 r 2 r 6 r 7 r 7 xxx xx x r 0 r 1 r 2 r 6 r 7 p 0 p 1 p 2 p 6 p 7 p 7 p 0 p 1 p 2 p 6 p 7 lp 0 p 1 p 2 p 6 p 7 xxx xx h hhh hh l = low logic level h = high logic level x = irrelevant p = present state r = previous state serial data out logic inputs dwg. ep-063-4 out v dd dmos power driver output dwg. ep-010-10 in v dd dwg. ep-063-5 out recommended operating conditions over operating temperature range logic supply voltage range, v dd ............... 4.5 v to 5.5 v high-level input voltage, v ih ............................ 0.85v dd low-level input voltage, v il ................................. 0.15v dd
6a595 8-bit serial-input, dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 4 limits characteristic symbol test conditions min. typ. max. units output breakdown v (br)dsx i o = 1 ma 50 v voltage off-state output i dsx v o = 40 v 0.1 1.0 a current v o = 40 v, t a = 125 c 0.2 5.0 a static drain-source r ds(on) i o = 350 ma 1.0 1.5 ? on-state resistance i o = 350 ma, t a = 125 c 1.7 2.5 ? source-drain v sd i f = 350 ma 0.9 1.1 v diode voltage nominal output i o(nom) v ds(on) = 0.5 v, t a = 85 c 350 ma current output current i o(chop) i o at which chopping starts, t c = 25 c 0.6 0.8 1.1 a logic input current i ih v i = v dd 1.0 a i il v i = 0 -1.0 a serial-data v oh i oh = -20 a 4.9 4.99 v output voltage i oh = -4 ma 4.5 4.7 v v ol i ol = 20 a 0 0.1 v i ol = 4 ma 0.3 0.5 v prop. delay time t plh i o = 350 ma, c l = 30 pf 100 ns t phl i o = 350 ma, c l = 30 pf 60 ns output rise time t r i o = 350 ma, c l = 30 pf 55 ns output fall time t f i o = 350 ma, c l = 30 pf 40 ns supply current i dd(off) outputs off 0.5 5.0 ma i dd(fclk) f clk = 5 mhz, c l = 30 pf, outputs off 1.3 ma typical data is at v dd = 5 v and is for design information only. note ?pulse test, duration 100 s, duty cycle 2%. electrical characteristics at t a = +25 c, v dd = 5 v, t ir = t if 10 ns (unless otherwise specified).
6a595 8-bit serial-input, dmos power driver www.allegromicro.com 5 timing requirements and specifications (logic levels are v dd and ground) clock serial data in strobe output enable out n dwg. wp-029-2 50% serial data out data data 50% 50% 50% c a b d e low = all outputs enabled p t data 50% p t low = output on high = output off output enable out n dwg. wp-030-2 data 10% 50% phl t plh t high = all outputs disabled 90% f t r t a. data active time before clock pulse (data set-up time), t su(d) .......................................... 20 ns b. data active time after clock pulse (data hold time), t h(d) .............................................. 20 ns c. clock pulse width, t w(clk) ............................................. 40 ns d. time between clock activation and strobe, t su(st) ....................................................... 50 ns e. strobe pulse width, t w(st) .............................................. 50 ns f. output enable pulse width, t w(oe) ................................ 4.5 s note ?timing is representative of a 12.5 mhz clock. higher speeds are attainable. serial data present at the input is transferred to the shift register on the rising edge of the clock input pulse. on succeeding clock pulses, the registers shift data information towards the serial data output. information present at any register is transferred to the respective latch on the rising edge of the strobe input pulse (serial-to-parallel conversion). when the output enable input is high, the output source drivers are disabled (off). the information stored in the latches is not affected by the output enable input. with the output enable input low, the outputs are controlled by the state of their respective latches. logic symbol 2 g3 c2 srg8 c1 r 1d 2 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 serial data out output enable strobe register clear serial data in clock dw g . fp-043-2
6a595 8-bit serial-input, dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 6 test circuit dwg. ep-066-2 out input i o v o t av i as = 600 ma v (br)dsx v o(on) 1 ? 210 mh +15 v dut single-pulse avalanche energy test circuit and waveforms e as = i as x v (br)dsx x t av /2 normal lamp in-rush current lamp current time current limit (chopping mode) on ~ 40 s off ~ 2.5 ms dwg. wp-008-1 not to scale i o(chop) chopping-mode operation high incandescent lamp turn-on currents (commonly called in-rush currents) can contribute to poor lamp reliability and destroy semiconductor lamp drivers. warming resistors protect both driver and lamp but use significant power when the lamp is off while current- limiting resistors waste power when the lamp is on. lamps with steady-state current ratings to 350 ma can be driven by the a6a595 without the need for warming or current limiting resistors. as shown (the dashed line), when an incandescent lamp is initially turned on, the cold filament is at mini- mum resistance and will normally allow a 10x peak in- rush current. as the lamp warms up, the filament resis- tance increases to its rated value and the lamp current is reduced to its steady-state rating. when switching a lamp with the a6a595, the internal chopping circuitry limits the current (the solid line) to i o(chop) . the device will stay in the chopping mode until the lamp resistance increases and the current requirement is less than i o(chop) . a side- effect of this current-limiting feature is that lamp turn-on time will increase.
6a595 8-bit serial-input, dmos power driver www.allegromicro.com 7 terminal descriptions A6A595KA a6a595klb (dip) (soic) terminal no. terminal no. terminal name function 1-2 1-2 out 2-3 current-sinking, open-drain dmos output terminals. 3 3 register clear when (active) low, the registers are cleared (set low). 4 4 output enable when (active) low, the output drivers are enabled; when high, all output drivers are turned off (blanked). 5-6 5-8 power ground reference terminal for output voltage measurements. 7 9 strobe data strobe input terminal; shift register data is latched on rising edge. 8 10 clock clock input terminal for data shift on rising edge. 9-12 11-14 out 4-7 current-sinking, open-drain dmos output terminals. 13 15 serial data out cmos serial-data output to the following shift register. 14 16 logic ground reference terminal for input voltage measurements. 15-16 17-20 power ground reference terminal for output voltage measurements. 17 21 logic supply (v dd ) the logic supply voltage (typically 5 v). 18 22 serial data in serial-data input to the shift-register. 19-20 23-24 out 0-1 current-sinking, open-drain dmos output terminals. note ?ower grounds must be connected together externally. 0 dwg. gp-073 50 150 100 case temperature in c -50 1.50 1.00 output current limit in amperes 0.50 0 v cc = 5.5 v 0.25 0.75 1.25 v cc = 4.5 v typical output current limit as a function of case temperature
6a595 8-bit serial-input, dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 8 A6A595KA dimensions in inches (controlling dimensions) dimensions in millimeters (for reference only) notes:1. exact body and lead configuration at vendor? option within limits shown. 2. lead spacing tolerance is non-cumulative 3. lead thickness is measured at seating plane or below. 0.014 0.008 0.300 bsc dwg. ma-001-20 in 0.430 max 20 1 10 0.280 0.240 0.210 max 0.070 0.045 0.015 min 0.022 0.014 0.100 bsc 0.005 min 0.150 0.115 11 1.060 0.980 0.355 0.204 7.62 bsc dwg. ma-001-20 mm 10.92 max 20 1 10 7.11 6.10 5.33 max 1.77 1.15 0.39 min 0.558 0.356 2.54 bsc 0.13 min 3.81 2.93 11 26.92 24.89
6a595 8-bit serial-input, dmos power driver www.allegromicro.com 9 a6a595klb dimensions in inches (for reference only) dimensions in millimeters (controlling dimensions) 0 to 8 1 2 3 0.2992 0.2914 0.6141 0.5985 0.491 0.394 0.020 0.013 0.0926 0.1043 0.0040 min . 0.0125 0.0091 dwg. ma-008-25 in 0.050 bsc 24 13 note 1 note 3 0.050 0.016 0 to 8 1 2 3 7.60 7.40 15.60 15.20 10.65 10.00 0.51 0.33 2.65 2.35 0.10 min . 0.32 0.23 dwg. ma-008-25a mm 1.27 bsc 24 13 note 1 note 3 1.27 0.40 notes: 1. webbed lead frame. leads 6, 7, 18, and 19 are internally one piece. 2. lead spacing tolerance is non-cumulative. 3. exact body and lead configuration at vendor? option within limits shown.
6a595 8-bit serial-input, dmos power driver 115 northeast cutoff, box 15036 worcester, massachusetts 01615-0036 (508) 853-5000 10 the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro products are not authorized for use as critical components in life-support devices or systems without express written approval. the information included herein is believed to be accurate and reliable. however, allegro microsystems, inc. assumes no responsi- bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.
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